module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);

    integer			i;
    
    wire	[31:0]	in1;
    
    always @(posedge clk) begin
        if(reset) begin
        	out <= 32'd0; 
        end
        else begin
            for(i = 0; i < 32; i=i+1) begin
                out[i] <= out[i] || (in1[i] & ~in[i]);
            end
        end
    end
    
    always @(posedge clk) begin
    	in1 <= in; 
    end
    
endmodule
